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Thank you for your interest in my research on "Single Cycle Access for Logic Test".

If you are interested in the technology, please read the original paper:

T. Strauch, "Single Cycle Access Structure for Logic Test", IEEE Trans. on VLSI, vol. 20, no. 5, May 2012, pp. 878-891 [link]

Identical copies of this paper have been published by:

[copy1] P. A. Selvakumar, and K.L.Hemalatha, "An Efficient Logic Test Structure For Low Power Testing", International Journal of Computer Applications in Engineering Sciences (IJCAES), Volume III, Special Issue, August 2013, ISSN: 2231-4946

[copy2] M. Sakthivel, and P. Selvakumar, "Priority Encoder Based Single Cycle Access Structure for Logic Test ", International Journal of Scientific & Engineering Research (IJSER), Volume 4, Issue 5, May-2013, ISSN 2229-5518

[copy3] Prasana P, and Viswanathan B, "Implementation of Single Cycle Access Structure for Logic Test", International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE), Vol. 2, Issue 4, April 2013, ISSN (Print) : 2320 – 3765

[copy4] U. Manimegala, B. Muthupandian, and R. Ganesan, "Power Optimization Technique for testing in VLSI Circuits", International Journal of Advanced Information Science and Technology (IJAIST), Vol. 2, No. 11, March 2013

[copy5] Sri Lakshmi Chandana, and B. Vamsi Krishna, "A Novel method to improve the Logic Test by using Single Cycle Access Structure", Int. Journal of Engineering Research and Applications (IJERA), Vol. 3, Issue 6, Nov-Dec, pp. 1721-1726

[copy6] K.Surya Kumari, Sneha M. Joseph, and V.N.M. Brahmanandam K., "A Static Time Analysis of 1-Bit to 32-Page SCA Architecture for Logic Test", International Journal of Science Engineering and Advance TEchnology (IJSEAT), Vol. 1, No. 7

[copy7] M.B. Bhemma Kumar, and V. Ravi Naik, "Logic Test of Single Cycle Access Structure", Intern. Journal of Scientific Research, Vol. 2, Issue 11, November 2013

[copy8] S. A. Ahmed, S. J. Badashah, and A. F. Hussain, "Chandra Shaker Pittala; J. Sravana; G. Ajitha; P. Saritha; Mohammad Khadir; V. Vijay, "Novel Methodology to Validate DUTs Using Single Access Structure", 2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 24-26 Sep. 2021, Kolkata, India

[copy9] C. Amarnath, and K.Bala, "A Logic Test to Minimize Test Data Volume By Single Cycle Access Structure", International Journal of Research in Computer and Cimmunication Technology, Vol. 3, Issue 9, September 2014

[copy10] C. Swapna, and D. Venkataramireddy, "VLSI Implementation of Single Cycle Access Structure for Logic Test in FPGA Technology", International Journal of Research in Advanced Engineering Technologies, Vol. 2, Issue 1, September 2014

[copy11] A. Joy, and S. John, "Dynamic Shift Scan with Area Efficiency", Intern. Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 5, Issue 3, March 2016

[copy12] G. M. Naik, and J. B. Naik, "An Efficient Novel Approach Paradigm of Single Cycle Switching Access Structure to Eliminate the Peak Power Consumption Problem", Journal of Advanced Research in Technology and Management Sciences, Vol. 01, Issue 03, November 2019

[copy13] C. S. Pittala, J. Sravana, G. Ajitha, and S. Lakshamanachari, V. Vijay, and S. C. Venkateswarlu, "Novel Architecture for Logic Test Using Single Cycle Access Structure", Journal of VLSI Circuits And Systems, Vol. 3, Issue 1, March 2021

[copy14] C. S. Pittala, J. Sravana, G. Ajitha, P. Saritha, Mohammad Khadir, and V. Vijay, "Novel Methodology to Validate DUTs Using Single Access Structure", 2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 24-26 Sep. 2021, Kolkata, India

Only [copy3, copy4 and copy6] follow the rule to mention the origin of the art in the reference section, although no value is added to the paper. All of them even copy over text, figures and tables, how ridiculous is that.